1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device having pads for a voltage stress test suitable for performing screening of defective chip areas by use of a probe card and prober in a wafer state.
2. Description of the Related Art
In a manufacturing process of a semiconductor device, after a wafer manufacturing process is finished, good chip areas are selected by a diesort test and defective chip areas are marked. Thereafter, good chip areas are contained in a package, and the shape of the final product is finished. Then, the semiconductor whose shape is finished as a final product and whose package is finished is burned-in.
In contrast, for performing screening of the defective chip areas by use of a probe card and a prober when the chip areas are in a wafer state before the diesort test, the following process is an ideal in view of the efficiency of the voltage stress test.
The needles of the probe card are simultaneously brought into contact with pads for a voltage stress test to be used in performing the screening of the defective goods on all IC chip areas on the wafer, and a voltage stress is applied thereto. In the above explanation, the terminals on the wafer are called as pads, and the terminals of the probe card are called as needles. However, any members may be used if they are structured to be electrically connected to each other.
However, in the present state of the probe card technique, it is impossible to simultaneously bring the needles of the probe card into contact with all chip areas on the wafer. In actual, it is preferable that the needles of the probe card be simultaneously brought into contact with the pads for voltage stress test on the chip areas on the wafer as much as possible. Therefore, it is preferable that the number of needles to be brought into contact with one chip area be the smallest as possible.
The following explains a case in which the voltage stress is applied to the chip areas by use of a power potential supply wire and a ground potential supply wire.
FIGS. 1 and 2 show a state that the needles of the probe card are brought into contact with two chip areas adjacent to each other among a plurality of IC chip areas on the wafer and the voltage stress is applied thereto when the conventional semiconductor device is burned-in in a wafer state.
In FIG. 1, three circuits 71a to 71c each having an independent electric power system are formed on each chip area 70. There are independently formed three VCC lines (power potential VCC supply wires) 72a to 72c to correspond to these circuits and three VSS lines (ground potential VSS supply wires) 73a to 73c. Three VCC pads 74a to 74c are formed to correspond to three VCC lines 72a to 72c, and three VSS pads 75a to 75c are formed to correspond to three VSS lines 73a to 73c.
The pads 74a to 74c and 75a to 75c are used such that the needles 76 projected from two sides of the probe card facing each other are simultaneously brought into contact with these pads and the voltage stress is applied the chip areas in a case that screening of the defective chip areas is performed by use of the probe card and the prober when the chip areas are in a wafer state before the diesort test.
Also, the pads 74a to 74c and 75a to 75c are used such that the needles 76 of the probe card are brought into contact with these pads at the time of the diesort test.
Moreover, the pads 74a to 74c and 75a to 75c are used such that these pads are bonded to outer pins (not shown) by a bonding wire when chips are separated from the semiconductor device in a wafer state and the respective separated chips are contained in the package.
For applying the voltage stress to the circuits 71a to 71c formed on the chip area 70 having three electric power systems by use of VCC lines 72a to 72c and VSS lines 73a to 73c in the wafer state, the necessary number of needles 76 of the probe card is six since the needles 76 must be simultaneously brought into contact with all pads, that is, VCC pads 74a to 74c and VSS pads 75a to 75c.
In a case that the circuit group having only one electric power system is formed on the chip area, since one VCC line and one VSS line, which are connected to the circuit group and one VCC pad and one VSS pad are provided, the number of the needles 76 may be two when applying the voltage stress in the wafer state.
Therefore, the necessary number of needles 76 of the former chip areas increases three times as many as that of the latter chip areas, so that the number of the chip areas with which the needles 76 can be brought into contact reduces to 1/3. In other words, the needles 76 of the probe cannot be brought into contact with all chip areas on the wafer due to the technical limitation of the number of the needles in the present technical state. Therefore, the efficiency of the voltage stress test to be applied to the wafer where the former chip area 70 is formed is reduced to 1/3 as compared with the wafer where the latter chip area is formed.
The efficiency of the voltage stress test is reduced as the number of the VCC lines 72a to 72c and that of VSS lines 73a to 73c and the number of the corresponding VCC pads 74a to 74c and that of VSS pads 75a to 75c are increased.
The following will explain some cases in which a plurality of VCC pads or VSS pads are formed on one chip area.
(A) In an IC chip contained in the package having one VCC pin or VSS pin, the electric power system are separated from the circuit group each being independent in the chip, the VCC pads or VSS pads are formed in each circuit, and bonded to one VCC pin or one VSS pin in a multiple fashion;
(B1) In an IC chip contained in the package having a plurality of VCC pins or VSS pins, the electric power system are separated from the circuit group each being independent in the chip, the VCC pads or VSS pads are formed in each circuit, the number of the VCC pads or VSS pads is larger than that of the VCC pins or VSS pins, and the VCC pads or VSS pads are bonded to an arbitrarily VCC pin or VSS pin in a multiple fashion;
(B2) In an IC chip contained in the package having a plurality of VCC pins or VSS pins, the electric power system are separated from the circuit group each being independent in the chip, the VCC pads or VSS pads are formed in each circuit, the number of the VCC pads or VSS pads is the same as that of the VCC pins or VSS pins, bonding pads are formed on the plurality of VCC lines or VSS lines, respectively, and bonded to the VCC pads or VSS pads, respectively.
(B3) In an IC chip contained in the package having a plurality of VCC pins or VSS pins, the electric power system are not separated, a plurality of bonding pads are formed on the VCC lines or VSS lines, respectively and bonded to the VCC pins or VSS pins, respectively, so as to lower the resistance of VCC lines or that of VSS lines.
Among the above cases (A) to (B3), in cases (A), (B1), and (B2), since the needles of the probe card must be in contact with the chip area by the number of VCC pads or VSS pads formed on the chip area, the efficiency of the voltage stress test is reduced.
On the other hand, in a chip area 80 shown in FIG. 2, pads 81a to 81c for stress test are formed separately from VCC pads 74a to 74c for bonding so as to correspond to the VCC lines 72a to 72c. Similarly, pads 82a to 82c for stress test are formed separately from VSS pads 75a to 75c for bonding so as to correspond to the VSS lines 73a to 73c.
As shown in FIG. 2, in the case that six pads 81a to 81c and 82a to 82c for voltage stress test are formed separately from the pads for bonding, the chip area will be increased by the number of six pads for voltage stress test.